/*******************************************************************************
*                                    ZLG
*                         ----------------------------
*                         innovating embedded platform
*
* Copyright (c) 2001-2021 Guangzhou ZHIYUAN Electronics Co., Ltd.
* All rights reserved.
*
* Contact information:
* web site:    https://www.zlg.cn
*******************************************************************************/
#ifndef __HC32F4A0_REGS_PWC_H
#define __HC32F4A0_REGS_PWC_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "hc32f4a0_regs_base.h"

/* \brief HC32F4A0 PWC 解锁代码*/
#define PWC_UNLOCK_CODE_0          (0xA501U)
#define PWC_UNLOCK_CODE_1          (0xA502U)
#define PWC_UNLOCK_CODE_2          (0xA508U)

/* \brief HC32F4A0 电源控制  功能保护控制寄存器位定义 */
/* \brief HC32F4A0 保护时钟控制器寄存器*/
#define PWC_FPRC_FPRCB0_POS        (0U)
#define PWC_FPRC_FPRCB0            (0x0001U)

#define PWC_FPRC_FPRCB1_POS        (1U)
#define PWC_FPRC_FPRCB1            (0x0002U)
#define PWC_FPRC_FPRCB2_POS        (2U)
#define PWC_FPRC_FPRCB2            (0x0004U)
#define PWC_FPRC_FPRCB3_POS        (3U)
#define PWC_FPRC_FPRCB3            (0x0008U)
#define PWC_FPRC_FPRCWE_POS        (8U)
#define PWC_FPRC_FPRCWE            (0xFF00U)

/* \brief HC32F4A0 功能时钟控制寄存器默认值*/
#define CLK_FCG0_DEFAULT           (0xFFFFFA0EUL)
#define CLK_FCG1_DEFAULT           (0xFFFFFFFFUL)
#define CLK_FCG2_DEFAULT           (0xFFFFFFFFUL)
#define CLK_FCG3_DEFAULT           (0xFFFFFFFFUL)

/* \brief HC32F4A0 PWC_FCG0PC寄存器位定义 */
#define PWC_FCG0PC_PRT0_POS        (0U)
#define PWC_FCG0PC_PRT0            (0x00000001UL)
#define PWC_FCG0PC_FCG0PCWE_POS    (16U)
#define PWC_FCG0PC_FCG0PCWE        (0xFFFF0000UL)

#define PWC_FCG0_AOS_POS           (17U)
#define PWC_FCG0_AOS               (0x00020000UL)

/* \brief HC32F4A0 PWC_FCG1寄存器位定义*/
#define PWC_FCG1_CAN1_POS          (0U)
#define PWC_FCG1_CAN1              (0x00000001UL)
#define PWC_FCG1_CAN2_POS          (1U)
#define PWC_FCG1_CAN2              (0x00000002UL)
#define PWC_FCG1_ETHER_POS         (2U)
#define PWC_FCG1_ETHER             (0x00000004UL)
#define PWC_FCG1_QSPI_POS          (3U)
#define PWC_FCG1_QSPI              (0x00000008UL)
#define PWC_FCG1_I2C1_POS          (4U)
#define PWC_FCG1_I2C1              (0x00000010UL)
#define PWC_FCG1_I2C2_POS          (5U)
#define PWC_FCG1_I2C2              (0x00000020UL)
#define PWC_FCG1_I2C3_POS          (6U)
#define PWC_FCG1_I2C3              (0x00000040UL)
#define PWC_FCG1_I2C4_POS          (7U)
#define PWC_FCG1_I2C4              (0x00000080UL)
#define PWC_FCG1_I2C5_POS          (8U)
#define PWC_FCG1_I2C5              (0x00000100UL)
#define PWC_FCG1_I2C6_POS          (9U)
#define PWC_FCG1_I2C6              (0x00000200UL)
#define PWC_FCG1_SDIOC1_POS        (10U)
#define PWC_FCG1_SDIOC1            (0x00000400UL)
#define PWC_FCG1_SDIOC2_POS        (11U)
#define PWC_FCG1_SDIOC2            (0x00000800UL)
#define PWC_FCG1_I2S1_POS          (12U)
#define PWC_FCG1_I2S1              (0x00001000UL)
#define PWC_FCG1_I2S2_POS          (13U)
#define PWC_FCG1_I2S2              (0x00002000UL)
#define PWC_FCG1_I2S3_POS          (14U)
#define PWC_FCG1_I2S3              (0x00004000UL)
#define PWC_FCG1_I2S4_POS          (15U)
#define PWC_FCG1_I2S4              (0x00008000UL)
#define PWC_FCG1_SPI1_POS          (16U)
#define PWC_FCG1_SPI1              (0x00010000UL)
#define PWC_FCG1_SPI2_POS          (17U)
#define PWC_FCG1_SPI2              (0x00020000UL)
#define PWC_FCG1_SPI3_POS          (18U)
#define PWC_FCG1_SPI3              (0x00040000UL)
#define PWC_FCG1_SPI4_POS          (19U)
#define PWC_FCG1_SPI4              (0x00080000UL)
#define PWC_FCG1_SPI5_POS          (20U)
#define PWC_FCG1_SPI5              (0x00100000UL)
#define PWC_FCG1_SPI6_POS          (21U)
#define PWC_FCG1_SPI6              (0x00200000UL)
#define PWC_FCG1_USBFS_POS         (22U)
#define PWC_FCG1_USBFS             (0x00400000UL)
#define PWC_FCG1_USBHS_POS         (23U)
#define PWC_FCG1_USBHS             (0x00800000UL)
#define PWC_FCG1_FMAC1_POS         (24U)
#define PWC_FCG1_FMAC1             (0x01000000UL)
#define PWC_FCG1_FMAC2_POS         (25U)
#define PWC_FCG1_FMAC2             (0x02000000UL)
#define PWC_FCG1_FMAC3_POS         (26U)
#define PWC_FCG1_FMAC3             (0x04000000UL)
#define PWC_FCG1_FMAC4_POS         (27U)
#define PWC_FCG1_FMAC4             (0x08000000UL)

/* \brief HC32F4A0 PWC_FCG2寄存器位定义*/
#define PWC_FCG2_TMR0_1_POS        (12U)
#define PWC_FCG2_TMR0_1            (0x00001000UL)

/* \brief HC32F4A0 PWC_FCG3寄存器位定义*/
#define PWC_FCG3_ADC1_POS          (0U)
#define PWC_FCG3_ADC1              (0x00000001UL)
#define PWC_FCG3_ADC2_POS          (1U)
#define PWC_FCG3_ADC2              (0x00000002UL)
#define PWC_FCG3_ADC3_POS          (2U)
#define PWC_FCG3_ADC3              (0x00000004UL)
#define PWC_FCG3_CMBIAS_POS        (3U)
#define PWC_FCG3_CMBIAS            (0x00000008UL)
#define PWC_FCG3_DAC1_POS          (4U)
#define PWC_FCG3_DAC1              (0x00000010UL)
#define PWC_FCG3_DAC2_POS          (5U)
#define PWC_FCG3_DAC2              (0x00000020UL)
#define PWC_FCG3_CMP1_POS          (8U)
#define PWC_FCG3_CMP1              (0x00000100UL)
#define PWC_FCG3_CMP2_POS          (9U)
#define PWC_FCG3_CMP2              (0x00000200UL)
#define PWC_FCG3_OTS_POS           (12U)
#define PWC_FCG3_OTS               (0x00001000UL)
#define PWC_FCG3_DVP_POS           (15U)
#define PWC_FCG3_DVP               (0x00008000UL)
#define PWC_FCG3_SMC_POS           (16U)
#define PWC_FCG3_SMC               (0x00010000UL)
#define PWC_FCG3_DMC_POS           (17U)
#define PWC_FCG3_DMC               (0x00020000UL)
#define PWC_FCG3_NFC_POS           (18U)
#define PWC_FCG3_NFC               (0x00040000UL)
#define PWC_FCG3_USART1_POS        (20U)
#define PWC_FCG3_USART1            (0x00100000UL)
#define PWC_FCG3_USART2_POS        (21U)
#define PWC_FCG3_USART2            (0x00200000UL)
#define PWC_FCG3_USART3_POS        (22U)
#define PWC_FCG3_USART3            (0x00400000UL)
#define PWC_FCG3_USART4_POS        (23U)
#define PWC_FCG3_USART4            (0x00800000UL)
#define PWC_FCG3_USART5_POS        (24U)
#define PWC_FCG3_USART5            (0x01000000UL)
#define PWC_FCG3_USART6_POS        (25U)
#define PWC_FCG3_USART6            (0x02000000UL)
#define PWC_FCG3_USART7_POS        (26U)
#define PWC_FCG3_USART7            (0x04000000UL)
#define PWC_FCG3_USART8_POS        (27U)
#define PWC_FCG3_USART8            (0x08000000UL)
#define PWC_FCG3_USART9_POS        (28U)
#define PWC_FCG3_USART9            (0x10000000UL)
#define PWC_FCG3_USART10_POS       (29U)
#define PWC_FCG3_USART10           (0x20000000UL)

/* \brief 电源控制，配置1掩码*/
#define PWC_FCG1_MASK                                                    \
                (PWC_FCG1_CAN1   | PWC_FCG1_CAN2 | PWC_FCG1_ETHER   |    \
                PWC_FCG1_QSPI    | PWC_FCG1_I2C1 | PWC_FCG1_I2C2    |    \
                PWC_FCG1_I2C3    | PWC_FCG1_I2C4 | PWC_FCG1_I2C5    |    \
                PWC_FCG1_I2C6    | PWC_FCG1_SDIOC1|PWC_FCG1_SDIOC2  |    \
                PWC_FCG1_I2S1    | PWC_FCG1_I2S2 | PWC_FCG1_I2S3    |    \
                PWC_FCG1_I2S4    | PWC_FCG1_SPI1 | PWC_FCG1_SPI2    |    \
                PWC_FCG1_SPI3    | PWC_FCG1_SPI4 | PWC_FCG1_SPI5    |    \
                PWC_FCG1_SPI6    | PWC_FCG1_USBFS| PWC_FCG1_USBHS   |    \
                PWC_FCG1_FMAC1   | PWC_FCG1_FMAC2| PWC_FCG1_FMAC3   |    \
                PWC_FCG1_FMAC4)
/* \brief 电源控制，配置2掩码*/
#define PWC_FCG2_MASK                                                    \
                (PWC_FCG2_TMR6_1| PWC_FCG2_TMR6_2 | PWC_FCG2_TMR6_3 |    \
                PWC_FCG2_TMR6_4 | PWC_FCG2_TMR6_5 | PWC_FCG2_TMR6_6 |    \
                PWC_FCG2_TMR6_7 | PWC_FCG2_TMR6_8 | PWC_FCG2_TMR4_1 |    \
                PWC_FCG2_TMR4_2 | PWC_FCG2_TMR4_3 | PWC_FCG2_HRPWM  |    \
                PWC_FCG2_TMR0_1 | PWC_FCG2_TMR0_2 | PWC_FCG2_EMB    |    \
                PWC_FCG2_TMR2_1 | PWC_FCG2_TMR2_2 | PWC_FCG2_TMR2_3 |    \
                PWC_FCG2_TMR2_4 | PWC_FCG2_TMRA_1 | PWC_FCG2_TMRA_2 |    \
                PWC_FCG2_TMRA_3 | PWC_FCG2_TMRA_4 | PWC_FCG2_TMRA_5 |    \
                PWC_FCG2_TMRA_6 | PWC_FCG2_TMRA_7 | PWC_FCG2_TMRA_8 |    \
                PWC_FCG2_TMRA_9 | PWC_FCG2_TMRA_10| PWC_FCG2_TMRA_11|    \
                PWC_FCG2_TMRA_12)
/* \brief 电源控制，配置3掩码*/
#define PWC_FCG3_MASK                                                    \
                (PWC_FCG3_ADC1   | PWC_FCG3_ADC2   | PWC_FCG3_ADC3   |   \
                 PWC_FCG3_DAC1   | PWC_FCG3_DAC2   | PWC_FCG3_CMP1   |   \
                 PWC_FCG3_CMP2   | PWC_FCG3_OTS    | PWC_FCG3_DVP    |   \
                 PWC_FCG3_SMC    | PWC_FCG3_DMC    | PWC_FCG3_NFC    |   \
                 PWC_FCG3_USART1 | PWC_FCG3_USART2 | PWC_FCG3_USART3 |   \
                 PWC_FCG3_USART4 | PWC_FCG3_USART5 | PWC_FCG3_USART6 |   \
                 PWC_FCG3_USART7 | PWC_FCG3_USART8 | PWC_FCG3_USART9 |   \
                 PWC_FCG3_USART10| PWC_FCG3_CMBIAS)

/* \brief HC32F4A0 电源控制相关寄存器定义*/
typedef struct {
    volatile uint32_t FCG0;
    volatile uint32_t FCG1;
    volatile uint32_t FCG2;
    volatile uint32_t FCG3;
    volatile uint32_t FCG0PC;
    uint8_t           RESERVED0[17436];
    volatile uint8_t  VBATRSTR;
    uint8_t           RESERVED1[15];
    volatile uint8_t  VBATCR;
    uint8_t           RESERVED2[15];
    volatile uint8_t  WKTC0;
    uint8_t           RESERVED3[3];
    volatile uint8_t  WKTC1;
    uint8_t           RESERVED4[3];
    volatile uint8_t  WKTC2;
    uint8_t           RESERVED5[423];
    volatile uint8_t  BKR0;
    uint8_t           RESERVED6[3];
    volatile uint8_t  BKR1;
    uint8_t           RESERVED7[3];
    volatile uint8_t  BKR2;
    uint8_t           RESERVED8[3];
    volatile uint8_t  BKR3;
    uint8_t           RESERVED9[3];
    volatile uint8_t  BKR4;
    uint8_t           RESERVED10[3];
    volatile uint8_t  BKR5;
    uint8_t           RESERVED11[3];
    volatile uint8_t  BKR6;
    uint8_t           RESERVED12[3];
    volatile uint8_t  BKR7;
    uint8_t           RESERVED13[3];
    volatile uint8_t  BKR8;
    uint8_t           RESERVED14[3];
    volatile uint8_t  BKR9;
    uint8_t           RESERVED15[3];
    volatile uint8_t  BKR10;
    uint8_t           RESERVED16[3];
    volatile uint8_t  BKR11;
    uint8_t           RESERVED17[3];
    volatile uint8_t  BKR12;
    uint8_t           RESERVED18[3];
    volatile uint8_t  BKR13;
    uint8_t           RESERVED19[3];
    volatile uint8_t  BKR14;
    uint8_t           RESERVED20[3];
    volatile uint8_t  BKR15;
    uint8_t           RESERVED21[3];
    volatile uint8_t  BKR16;
    uint8_t           RESERVED22[3];
    volatile uint8_t  BKR17;
    uint8_t           RESERVED23[3];
    volatile uint8_t  BKR18;
    uint8_t           RESERVED24[3];
    volatile uint8_t  BKR19;
    uint8_t           RESERVED25[3];
    volatile uint8_t  BKR20;
    uint8_t           RESERVED26[3];
    volatile uint8_t  BKR21;
    uint8_t           RESERVED27[3];
    volatile uint8_t  BKR22;
    uint8_t           RESERVED28[3];
    volatile uint8_t  BKR23;
    uint8_t           RESERVED29[3];
    volatile uint8_t  BKR24;
    uint8_t           RESERVED30[3];
    volatile uint8_t  BKR25;
    uint8_t           RESERVED31[3];
    volatile uint8_t  BKR26;
    uint8_t           RESERVED32[3];
    volatile uint8_t  BKR27;
    uint8_t           RESERVED33[3];
    volatile uint8_t  BKR28;
    uint8_t           RESERVED34[3];
    volatile uint8_t  BKR29;
    uint8_t           RESERVED35[3];
    volatile uint8_t  BKR30;
    uint8_t           RESERVED36[3];
    volatile uint8_t  BKR31;
    uint8_t           RESERVED37[3];
    volatile uint8_t  BKR32;
    uint8_t           RESERVED38[3];
    volatile uint8_t  BKR33;
    uint8_t           RESERVED39[3];
    volatile uint8_t  BKR34;
    uint8_t           RESERVED40[3];
    volatile uint8_t  BKR35;
    uint8_t           RESERVED41[3];
    volatile uint8_t  BKR36;
    uint8_t           RESERVED42[3];
    volatile uint8_t  BKR37;
    uint8_t           RESERVED43[3];
    volatile uint8_t  BKR38;
    uint8_t           RESERVED44[3];
    volatile uint8_t  BKR39;
    uint8_t           RESERVED45[3];
    volatile uint8_t  BKR40;
    uint8_t           RESERVED46[3];
    volatile uint8_t  BKR41;
    uint8_t           RESERVED47[3];
    volatile uint8_t  BKR42;
    uint8_t           RESERVED48[3];
    volatile uint8_t  BKR43;
    uint8_t           RESERVED49[3];
    volatile uint8_t  BKR44;
    uint8_t           RESERVED50[3];
    volatile uint8_t  BKR45;
    uint8_t           RESERVED51[3];
    volatile uint8_t  BKR46;
    uint8_t           RESERVED52[3];
    volatile uint8_t  BKR47;
    uint8_t           RESERVED53[3];
    volatile uint8_t  BKR48;
    uint8_t           RESERVED54[3];
    volatile uint8_t  BKR49;
    uint8_t           RESERVED55[3];
    volatile uint8_t  BKR50;
    uint8_t           RESERVED56[3];
    volatile uint8_t  BKR51;
    uint8_t           RESERVED57[3];
    volatile uint8_t  BKR52;
    uint8_t           RESERVED58[3];
    volatile uint8_t  BKR53;
    uint8_t           RESERVED59[3];
    volatile uint8_t  BKR54;
    uint8_t           RESERVED60[3];
    volatile uint8_t  BKR55;
    uint8_t           RESERVED61[3];
    volatile uint8_t  BKR56;
    uint8_t           RESERVED62[3];
    volatile uint8_t  BKR57;
    uint8_t           RESERVED63[3];
    volatile uint8_t  BKR58;
    uint8_t           RESERVED64[3];
    volatile uint8_t  BKR59;
    uint8_t           RESERVED65[3];
    volatile uint8_t  BKR60;
    uint8_t           RESERVED66[3];
    volatile uint8_t  BKR61;
    uint8_t           RESERVED67[3];
    volatile uint8_t  BKR62;
    uint8_t           RESERVED68[3];
    volatile uint8_t  BKR63;
    uint8_t           RESERVED69[3];
    volatile uint8_t  BKR64;
    uint8_t           RESERVED70[3];
    volatile uint8_t  BKR65;
    uint8_t           RESERVED71[3];
    volatile uint8_t  BKR66;
    uint8_t           RESERVED72[3];
    volatile uint8_t  BKR67;
    uint8_t           RESERVED73[3];
    volatile uint8_t  BKR68;
    uint8_t           RESERVED74[3];
    volatile uint8_t  BKR69;
    uint8_t           RESERVED75[3];
    volatile uint8_t  BKR70;
    uint8_t           RESERVED76[3];
    volatile uint8_t  BKR71;
    uint8_t           RESERVED77[3];
    volatile uint8_t  BKR72;
    uint8_t           RESERVED78[3];
    volatile uint8_t  BKR73;
    uint8_t           RESERVED79[3];
    volatile uint8_t  BKR74;
    uint8_t           RESERVED80[3];
    volatile uint8_t  BKR75;
    uint8_t           RESERVED81[3];
    volatile uint8_t  BKR76;
    uint8_t           RESERVED82[3];
    volatile uint8_t  BKR77;
    uint8_t           RESERVED83[3];
    volatile uint8_t  BKR78;
    uint8_t           RESERVED84[3];
    volatile uint8_t  BKR79;
    uint8_t           RESERVED85[3];
    volatile uint8_t  BKR80;
    uint8_t           RESERVED86[3];
    volatile uint8_t  BKR81;
    uint8_t           RESERVED87[3];
    volatile uint8_t  BKR82;
    uint8_t           RESERVED88[3];
    volatile uint8_t  BKR83;
    uint8_t           RESERVED89[3];
    volatile uint8_t  BKR84;
    uint8_t           RESERVED90[3];
    volatile uint8_t  BKR85;
    uint8_t           RESERVED91[3];
    volatile uint8_t  BKR86;
    uint8_t           RESERVED92[3];
    volatile uint8_t  BKR87;
    uint8_t           RESERVED93[3];
    volatile uint8_t  BKR88;
    uint8_t           RESERVED94[3];
    volatile uint8_t  BKR89;
    uint8_t           RESERVED95[3];
    volatile uint8_t  BKR90;
    uint8_t           RESERVED96[3];
    volatile uint8_t  BKR91;
    uint8_t           RESERVED97[3];
    volatile uint8_t  BKR92;
    uint8_t           RESERVED98[3];
    volatile uint8_t  BKR93;
    uint8_t           RESERVED99[3];
    volatile uint8_t  BKR94;
    uint8_t           RESERVED100[3];
    volatile uint8_t  BKR95;
    uint8_t           RESERVED101[3];
    volatile uint8_t  BKR96;
    uint8_t           RESERVED102[3];
    volatile uint8_t  BKR97;
    uint8_t           RESERVED103[3];
    volatile uint8_t  BKR98;
    uint8_t           RESERVED104[3];
    volatile uint8_t  BKR99;
    uint8_t           RESERVED105[3];
    volatile uint8_t  BKR100;
    uint8_t           RESERVED106[3];
    volatile uint8_t  BKR101;
    uint8_t           RESERVED107[3];
    volatile uint8_t  BKR102;
    uint8_t           RESERVED108[3];
    volatile uint8_t  BKR103;
    uint8_t           RESERVED109[3];
    volatile uint8_t  BKR104;
    uint8_t           RESERVED110[3];
    volatile uint8_t  BKR105;
    uint8_t           RESERVED111[3];
    volatile uint8_t  BKR106;
    uint8_t           RESERVED112[3];
    volatile uint8_t  BKR107;
    uint8_t           RESERVED113[3];
    volatile uint8_t  BKR108;
    uint8_t           RESERVED114[3];
    volatile uint8_t  BKR109;
    uint8_t           RESERVED115[3];
    volatile uint8_t  BKR110;
    uint8_t           RESERVED116[3];
    volatile uint8_t  BKR111;
    uint8_t           RESERVED117[3];
    volatile uint8_t  BKR112;
    uint8_t           RESERVED118[3];
    volatile uint8_t  BKR113;
    uint8_t           RESERVED119[3];
    volatile uint8_t  BKR114;
    uint8_t           RESERVED120[3];
    volatile uint8_t  BKR115;
    uint8_t           RESERVED121[3];
    volatile uint8_t  BKR116;
    uint8_t           RESERVED122[3];
    volatile uint8_t  BKR117;
    uint8_t           RESERVED123[3];
    volatile uint8_t  BKR118;
    uint8_t           RESERVED124[3];
    volatile uint8_t  BKR119;
    uint8_t           RESERVED125[3];
    volatile uint8_t  BKR120;
    uint8_t           RESERVED126[3];
    volatile uint8_t  BKR121;
    uint8_t           RESERVED127[3];
    volatile uint8_t  BKR122;
    uint8_t           RESERVED128[3];
    volatile uint8_t  BKR123;
    uint8_t           RESERVED129[3];
    volatile uint8_t  BKR124;
    uint8_t           RESERVED130[3];
    volatile uint8_t  BKR125;
    uint8_t           RESERVED131[3];
    volatile uint8_t  BKR126;
    uint8_t           RESERVED132[3];
    volatile uint8_t  BKR127;
    uint8_t           RESERVED133[1027];
    volatile uint8_t  PWRC0;
    uint8_t           RESERVED134[3];
    volatile uint8_t  PWRC1;
    uint8_t           RESERVED135[3];
    volatile uint8_t  PWRC2;
    uint8_t           RESERVED136[3];
    volatile uint8_t  PWRC3;
    uint8_t           RESERVED137[3];
    volatile uint8_t  PWRC4;
    uint8_t           RESERVED138[3];
    volatile uint8_t  PVDCR0;
    uint8_t           RESERVED139[3];
    volatile uint8_t  PVDCR1;
    uint8_t           RESERVED140[3];
    volatile uint8_t  PVDFCR;
    uint8_t           RESERVED141[3];
    volatile uint8_t  PVDLCR;
    uint8_t           RESERVED142[7];
    volatile uint8_t  PDWKE0;
    uint8_t           RESERVED143[3];
    volatile uint8_t  PDWKE1;
    uint8_t           RESERVED144[3];
    volatile uint8_t  PDWKE2;
    uint8_t           RESERVED145[3];
    volatile uint8_t  PDWKES;
    uint8_t           RESERVED146[3];
    volatile uint8_t  PDWKF0;
    uint8_t           RESERVED147[3];
    volatile uint8_t  PDWKF1;
    uint8_t           RESERVED148[163];
    volatile uint32_t RAMPC0;
    volatile uint16_t RAMOPM;
    uint8_t           RESERVED149[2];
    volatile uint32_t PRAMLPC;
    uint8_t           RESERVED150[4];
    volatile uint8_t  PVDICR;
    uint8_t           RESERVED151[3];
    volatile uint8_t  PVDDSR;
    uint8_t           RESERVED152[29463];
    volatile uint16_t STPMCR;
    uint8_t           RESERVED153[1008];
    volatile uint16_t FPRC;
} hc32f4a0_pwc_regs_t;

#define HC32F4A0_PWC    ((hc32f4a0_pwc_regs_t *)HC32F4A0_PWC_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */

#endif
